Gate Formation Memory by Planarization

ABSTRACT

Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization.

This application is a Continuation of U.S. patent application Ser. No.14/136,358, filed Dec. 20, 2013, which is incorporated by referenceherein in its entirety.

TECHNICAL FIELD

This disclosure relates generally to improved semiconductor devices andmethods for making such devices.

RELATED ART

A non-volatile memory, such as Flash memory, retains stored data even ifpower to the memory is removed. A non-volatile memory cell stores data,for example, by storing electrical charge in an electrically isolatedfloating gate or in a charge-trapping layer underlying a control gate ofa field-effect transistor (FET). The stored electrical charge controlsthe threshold of the FET, thereby controlling the memory state of thecell.

A non-volatile memory cell is programmed using, for example, hot carrierinjection to place charge into a storage layer. High drain and gatevoltages are used to facilitate the programming process, and the memorycell conducts relatively high current during programming, which can beundesirable in low voltage or low power application.

A split-gate memory cell is a type of non-volatile memory cell, in whicha select gate is placed adjacent a memory gate. During programming of asplit-gate memory cell, the select gate is biased at a relatively lowvoltage, and only the memory gate is biased at the high voltage toprovide the vertical electric field necessary for hot-carrier injection.Since acceleration of the carriers takes place in the channel regionmostly under the select gate, the relatively low voltage on the selectgate results in more efficient carrier acceleration in the horizontaldirection compared to a conventional Flash memory cell. That makeshot-carrier injection more efficient with lower current and lower powerconsumption during programming operation. A split-gate memory cell maybe programmed using techniques other than hot-carrier injection, anddepending on the technique, any advantage over the conventional Flashmemory cell during programming operation may vary.

Fast read time is another advantage of a split-gate memory cell. Theerased state of the memory gate can be near or in depletion mode (i.e.,threshold voltage, Vt, less than zero volt) because the select gate isin series with the memory gate. Even when the erased memory gate is insuch depletion mode, the select gate in the off state prevents theChannel from conducting substantial current. The threshold voltage inthe erase state is established near or below zero, which allows a lowthe threshold voltage in the programmed state, yielding reasonable readmargin between erase and program states. The voltages applied to bothselect gate and memory gate in read operation can be less than or equalto the supply voltage. Thus, the read operation is faster because thesupply voltage need not be pumped to a high level.

It is common to monolithically incorporate multiple types offield-effect devices on the same substrate as memory cells. Thosenon-memory devices perform, for example, decoding, charge-pumping, andother functions related to memory operations. The substrate may alsoinclude non-memory devices to provide functions that are not related tomemory operations. Such non-memory devices incorporated on the samesubstrate as the memory cells may include transistors tailored forhigh-speed operations, while other transistors are tailored for handlinghigh operating voltages. Integrating the processing of memory cells,such as a split-gate memory cell, with the processing of one or moretypes of non-memory transistors on the same substrate is challenging aseach requires different fabrication parameters. Accordingly, there is aneed for device and methods for integrating a memory cell and otherdevices on the same substrate, to facilitate improved cost, performance,reliability, or manufacturability.

BRIEF SUMMARY OF THE INVENTION

A semiconductor device and methods of forming the semiconductor deviceare disclosed herein. According to embodiments of the method, the deviceis formed by forming a gate structure on a substrate. The gate structureincludes a charge trapping dielectric formed between the substrate and afirst poly layer. A top dielectric is formed over the poly layer, and asidewall dielectric may be formed on a side of the poly layer. A secondpoly layer can be formed over the gate structure such that the secondpoly layer includes a vertical portion that is in contact with thesidewall dielectric, and a top portion that is in contact with the topdielectric. The top portion of the second poly layer is then be removed.

According to various embodiments, the semiconductor device includes asubstrate and a gate structure. The gate structure can he formed on thesubstrate. The gate structure includes a charge trapping dielectric thatis formed between the substrate and a first poly layer and a sidewalldielectric and formed on a side of the poly layer. A second poly layeris formed adjacent to the gate structure. The second poly layer includesa vertical portion in contact with the sidewall dielectric and has a topportion that is substantially flat.

Further features and advantages of embodiments of the invention, as wellas the structure and operation of various embodiments of the invention,are described in detail below with reference to the accompanyingdrawings. It is noted that the invention is not limited to the specificembodiments described herein. Such embodiments are presented herein forillustrative purposes only. Additional embodiments will be apparent to aperson skilled in the relevant art(s) based on the teachings containedherein.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGS.

Embodiments of the invention will now be described, by way of exampleonly, with reference to the accompanying schematic drawings in whichcorresponding reference symbols indicate corresponding parts. Further,the accompanying drawings, which are incorporated herein and form partof the specification, illustrate embodiments of the present invention,and, together with the description, further serve to explain theprinciples of the invention and to enable a person skilled in therelevant art(s) to make and use the invention.

FIG. 1 depicts a cross-section of a split-gate memory cell according tovarious embodiments.

FIG. 2 is a circuit diagram of a memory cell in a memory array accordingto various embodiments.

FIG. 3 depicts a cross-section of a semiconductor device according tovarious embodiments.

FIG. 4 is a functional block diagram of a memory device according tovarious embodiments.

FIGS. 5A-5G depict cross sections of an exemplary semiconductor deviceat various points during its manufacture according to variousembodiments.

FIG. 6 is a flowchart depicting a method of manufacturing asemiconductor device according to various embodiments.

The features and advantages of embodiments of the present invention willbecome more apparent from the detailed description set forth below whentaken in conjunction with the drawings. In the drawings, like referencenumbers generally indicate identical, functionally similar, and/orstructurally similar elements.

DETAILED DESCRIPTION OF THE INVENTION

It is to be appreciated that the Detailed Description section, and notthe Summary and Abstract sections, is intended to be used to interpretthe claims. The Summary and Abstract sections may set forth one or morebut not all exemplary embodiments of the present invention ascontemplated by the inventor(s), and thus, are not intended to limit thepresent invention and the appended claims in any way.

This specification discloses one or more embodiments that incorporatethe features of this invention. The disclosed embodiment(s) merelyexemplify the present invention. The scope of the present invention isnot limited to the disclosed embodiment(s). The present invention isdefined by the claims appended hereto.

The embodiment(s) described, and references in the specification to “oneembodiment,” “an embodiment,” “an example embodiment,” etc., indicatethat the embodiment(s) described may include a particular feature,structure, or characteristic, but every embodiment may not necessarilyinclude the particular feature, structure, or characteristic. Moreover,such phrases are not necessarily referring to the same embodiment.Further, when a particular feature, structure, or characteristic isdescribed in connection with an embodiment, it is understood that it iswithin the knowledge of one skilled in the art to effect such feature,structure, or characteristic in connection with other embodimentswhether or not explicitly described.

Before describing the various embodiments in more detail, furtherexplanation shall be given regarding certain terms that may be usedthroughout the descriptions.

The term “etch” or “etching” is used herein to generally describe afabrication process of patterning a material, such that at least aportion of the material remains after the etch is completed. Forexample, it should be understood that the process of etching siliconinvolves the steps of patterning a masking layer (e.g., photoresist or ahard mask) above the silicon, and then removing the areas of silicon nolonger protected by the masking layer. As such, the areas of siliconprotected by the mask would remain behind after the etch process iscomplete. However, in another example, etching may also refer to aprocess that does not use a mask, but still leaves behind at least aportion of the material after the etch process is complete.

The above description serves to distinguish the term “etching” from“removing.” When etching a material, at least a portion of the materialremains behind after the process is completed. In contrast, whenremoving a material, substantially all of the material is removed in theprocess. However, in some embodiments, ‘removing’ is considered to be abroad term that may incorporate etching.

During the descriptions herein, various regions of the substrate uponwhich the field-effect devices are fabricated are mentioned. It shouldbe understood that these regions may exist anywhere on the substrate andfurthermore that the regions may not be mutually exclusive. That is, insome embodiments, portions of one or more regions may overlap. Althoughup to three different regions are described herein, it should beunderstood that any number of regions may exist on the substrate and maydesignate areas having certain types of devices or materials. Ingeneral, the regions are used to conveniently describe areas of thesubstrate that include similar devices and should not limit the scope orspirit of the described embodiments.

The terms “forming,” “form,” “deposit,” or “dispose” are used herein todescribe the act of applying a layer of material to the substrate. Suchterms are meant to describe any possible layer-forming techniqueincluding, but not limited to, thermal growth, sputtering, evaporation,chemical vapor deposition, epitaxial growth, electroplating, etc.According to various embodiments, for instance, deposition may beperformed according to any appropriate well-known method. For instance,deposition can comprise any process that grows, coats, or transfersmaterial onto a substrate. Some well-known technologies include physicalvapor deposition (PVD), chemical vapor deposition (CVD), electrochemicaldeposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition(ALD), and plasma-enhanced CVD (PECVD), amongst others.

The “substrate” as used throughout the descriptions is most commonlythought to be silicon. However, the substrate may also be any of a widearray of semiconductor materials such as germanium, gallium arsenide,indium phosphide, etc. In other embodiments, the substrate may beelectrically non-conductive such as a glass or sapphire wafer.

As used herein, “mask” may comprise any appropriate material that allowsfor selective removal (e.g., etching) of an unmasked portion a material.According to some embodiments, masking structures may comprise aphotoresist such as Poly(methyl methacrylate) (PMMA), Poly(methylglutarimide) (PMG), a Phenol formaldehyde resin, a suitable epoxy, etc.

Before describing such embodiments in more detail, it is instructive topresent an example memory cell and environment in which the presentembodiments may be implemented.

FIG. 1 illustrates an example of a split-gate non-volatile memory cell100. Memory cell 100 is formed on a substrate 102, such as silicon.Substrate 102 is commonly p-type or a p-type well while a first dopedsource/drain region 104 and a second doped source/drain region 106 aren-type. However, it is also possible for substrate 102 to be n-typewhile regions 104 and 106 are p-type.

Memory cell 100 includes two gates, a select gate 108 and a memory gate110. Each gate may comprise: a gate conductor such as a doped poly layerformed by well known, fix example, deposit and etch techniques to definethe gate structure. Select gate 108 is disposed over a dielectric layer112. Memory gate 110 is disposed over a charge trapping dielectric 114having one or more dielectric layers. In one example, charge trappingdielectric 114 includes a charge trapping silicon nitride layersandwiched between two silicon dioxide layers to create a three-layerstack collectively and commonly referred to as “ONO.” Other chargetrapping dielectrics may include a silicon-rich nitride film, or anyfilm that includes, but is not limited to, silicon, oxygen, and nitrogenin various stoichiometries. A vertical dielectric 116 is also disposedbetween select gate 108 and memory gate 110 for electrical isolationbetween the two gates. In some examples, vertical dielectric 116 andcharge trapping dielectric 114 are the same dielectric, while otherexamples form one dielectric before the other (e.g., they can havedifferent dielectric properties.) As such, vertical dielectric 116 neednot include the same film structure as charge trapping dielectric 114,regions 104 and 106 are created by implanting dopants using, forexample, an ion implantation technique. Regions 104 and 106 form thesource or drain of the split-gate transistor depending on whatpotentials are applied to each. In split gate transistors, forconvenience, region 104 is commonly referred to as the drain, whileregion 106 is commonly referred to as the source, independent of therelative biases. It is to be understood that this description is meantto provide a general overview of a common split-gate architecture andthat, in actual practice, many more detailed steps and layers areprovided to form the final memory cell 100.

An example write, read, and erase operation will now be described as itrelates to memory cell 100. To order write a bit in memory cell 100, apositive voltage on the order of 5 volts, for example, is applied toregion 106 while region 104 and substrate 102 are grounded. A lowpositive voltage on the order of 1.5 volts, for example, is applied toselect gate 108 while a higher positive voltage on the order of 8 volts,for example, is applied to memory gate 110. As electrons are acceleratedwithin a channel region between the source and drain, some of them willacquire sufficient energy to be injected upwards and get trapped insidecharge trapping dielectric 114. This is known hot electron injection. Inone example of charge trapping dielectric 114, the electrons are trappedwithin a nitride layer of charge trapping dielectric. 114. This nitridelayer is also commonly referred to as the charge trapping layer. Thetrapped charge within charge trapping dielectric 114 store the “high”bit within memory cell 100, even after the various supply voltages areremoved.

In order to “erase” the stored charge within memory cell 100 and returnthe state of memory cell 100 to a “low” bit, a positive voltage on theorder of 5 volts, for example, is applied to region 106 while region 104is floated or at a certain bias, and select gate 108 and 102 aretypically grounded. A high negative voltage on the order of −8 volts,for example, is applied to memory gate 110. The bias conditions betweenmemory gate 110 and region 106 generate holes through band-to-bandtunneling. The generated holes are sufficiently energized by the strongelectric field under memory gate 110 and are injected upwards intocharge trapping dielectric 114. The injected holes effectively erase thememory cell 100 to the “low” bit state.

In order to “read” the stored bit of memory cell 100, a low voltage isapplied to each of the select gate, memory gate, and region 104 in therange between zero and three volts, for example, while region 106 andsubstrate 102 are typically grounded. The low voltage applied to thememory gate is chosen so that it lies substantially equidistant betweenthe threshold voltage necessary to turn on the transistor when storing a“high” bit and the threshold voltage necessary to turn on the transistorwhen storing a “low” bit in order to clearly distinguish between the twostates. For example, if the application of the low voltage during the“read” operation caused substantial current to flow between regions 104and 106, there, the memory cell holds a “low” bit and if the applicationof the low voltage during the “read” operation does not causesubstantial current to flow between regions 104 and 106, then the memorycell holds a “high” bit.

FIG. 2 illustrates an example circuit diagram 200 that comprises amemory cell 100 including connections to various metal layers in asemiconductor device. Only a single memory cell 100 is illustrated,however, as evidenced by the ellipses in both the X and Y direction, anarray of memory cells may be connected by the various lines running inboth the X and Y directions. In this way, one or more memory cells 100may be selected for reading, writing, and erasing bits based on the bitline (BL) and source line (SL) used.

An example source line (SL) runs along the X direction and is formed ina first metal layer (M1). Source line (SL) may be used to makeelectrical connection with doped region 106 of each memory cell 100along a row extending in the X direction.

An example bit line (BL) runs along the Y direction and is formed in asecond metal layer (M2). Bit line (BL) may be used to make electricalconnection with doped region 104 of each memory cell 100 along a columnextending in the Y direction.

It is to be understood that the circuit connections shown in FIG. 2 areonly exemplary and that the various connections could be made indifferent metal layers than those illustrated. Furthermore, although notdepicted, memory cells 100 may be arrayed in the Z direction as wellformed within multiple stacked layers.

FIG. 3 illustrates an example semiconductor device 300 that includesboth memory circuitry 302 and peripheral circuitry 304 in the samesubstrate 102. In this example, substrate 102 includes a core region 302and a periphery region 304. Core region 302 includes a plurality ofmemory cells 100 that may operate similarly to those previouslydescribed. It should be understood that the cross-section of FIG. 3 isonly exemplary, and that core region 302 and periphery region 304 may belocated in any area of substrate 102 and may be made up of variousdifferent regions. Furthermore, core region 302 and periphery region 304may exist in the same general area of substrate 102.

Substrate 302—and indeed substrates in general as used throughout thedescription—can be silicon according to various embodiments. However,the substrate 302 may also be any of a wide array of semiconductormaterials such as germanium, gallium arsenide, indium phosphide, etc. Inother embodiments, the substrate 302 may be electrically non-conductivesuch as a glass or sapphire wafer,

Periphery region 304 may include integrated circuit components such asresistors, capacitors, inductors, etc., as well as transistors. In theillustrated embodiment, periphery region 304 includes a plurality ofhigh-voltage transistors 306 and low-voltage transistors 308. In oneexample, high-voltage transistors 306 exist in a separate region ofsubstrate 102 than low-voltage transistors 308. High-voltage transistors306 are capable of handling voltages up to 20 volts in magnitude, forexample, while low-voltage transistors 308 operate at a faster speed,but cannot operate at the same high voltages as high-voltage transistors306. In an embodiment, low voltage transistors 308 are designed to havea shorter gate length than high voltage transistors 306. High-voltagetransistors 306 are commonly characterized as having a thicker gatedielectric 310 than the gate dielectric of low-voltage transistors 308.As shown in FIG. 3, low voltage transistors 308 have a narrower widththan high-voltage transistors 306, but this need not be the case.According to some embodiments, low-voltage 308 transistors can be widerthan high voltage transistors 306 or, alternatively, low-voltagetransistors 308 and high-voltage transistors 306 can have the samewidth.

During the descriptions herein, various regions of the substrate uponwhich the field-effect devices are fabricated are mentioned. Forinstance, with respect to FIG. 3, core region 302 and periphery region304 were described. It should be understood that these regions may existanywhere on the substrate and furthermore that the regions may not bemutually exclusive. That is, in some embodiments, portions of one ormore regions may overlap. Although up to three different regions aredescribed herein, it should be understood that any number of regions mayexist on the substrate and may designate areas having certain types ofdevices or materials. In general, the regions are used to convenientlydescribe areas of the substrate that include similar devices and shouldnot limit the scope or spirit of the described embodiments.

FIG. 4 is a functional block diagram of a memory device 402 according toembodiments of the present invention. As shown, memory device 402includes a memory array 404, high voltage control logic 406, and lowvoltage control logic 408. According to various embodiments, the memoryarray 404 may comprise a number of memory cells 100 and may bephysically located in a core region 302 of memory device 402. Highvoltage control logic 406 may comprise a number of high-voltagetransistors 306, which can be used to control and/or drive portions ofthe memory array 404. Additionally, the high voltage control logic 406may be physically located in the periphery 304 of the memory device 402.Similarly to the high voltage control logic 406, the low voltage controllogic 408 may comprise a number of low voltage transistors 308, whichcan be used to control and/or drive portions of the memory array 404.The low voltage control logic 408 may also be located in the periphery304 of the memory device. According to various embodiments, the highvoltage control logic 406 and the low voltage control logic 408 arelocated in different portions of the periphery region 304.

FIGS. 5A-5G depict a cross section of a semiconductor device 500 atvarious points in its manufacture according to various embodiments. FIG.5A depicts device 500 after a number of structures have been formed. Asshown in FIG. 5A, the device 500 includes gate structures 522 a and 522b (collectively 522) formed over a substrate 502, Each of gatestructures 522 a and 522 b is formed over a charge trapping dielectric504, itself, may comprise several layers 504 a, 504 b, and 504 c. Eachof the layers 504 a, 504 b, and 504 c of the charge trapping dielectric504 may comprise any suitable dielectric material such as, for instancean oxide. According to various embodiments the layer's 504 a, 504 b, and504 c may be different thicknesses, but this need not be the case—indeedaccording to various embodiments some or all of the layers 504 a, 504 b,and 504 c may be the same thickness. Charge trapping dielectric 504 maybe formed through any well-known method. For instance, the dielectric504 is grown on the substrate 502 and comprise an oxide of the substratematerial (e.g., silicon oxide). It is also possible, however, for thecharge trapping 504 dielectric to be disposed on the substrate andcomprises an oxide of a different material than the substrate.Additionally, the charge trapping dielectric may comprise the same ordifferent material and may be formed at the same time or at differenttimes according to various embodiments. According to variousembodiments, the charge trapping dielectric 504 comprises one or morelayers of dielectric such as ONO, as described above. For instance, thecharge trapping dielectric 504 may comprise a first dielectric layer 504aa, a charge trapping layer 504 b, and a second dielectric layer 504 c.Regardless of the specific composition of the charge trapping dielectric504, it preferably contains at least one charge trapping layer 504 b.Such a charge trapping layer is formed of a nitride or silicon richnitride, and may include multiple layers of different nitrides accordingto some embodiments.

Each of the gate structures 522 a and 522 b includes a conductor layer506 a and 506 b (collectively referred to as 506). The conductor layer506 is disposed or deposited according to any appropriate well-knownmethod such as deposition. Deposition may comprise any process thatgrows, coats, or transfers material onto a substrate. Some well-knowntechnologies it elude physical vapor deposition (PVD), chemical vapordeposition (CVD), electrochemical deposition (LCD), molecular beamepitaxy (MBE), atomic layer deposition (AID), and plasma-enhanced CVD(PECVD), amongst others.

A cap layer 508 a and 508 b (collectively 508) is formed of conductivelayers 506 a and 506 b in each of the gate structures 522 a and 522 b.According to various embodiments, the cap layer 508 comprises adialectic such as nitride.

FIG. 5B depicts semiconductor device 500 at a different point in itsmanufacture according to various embodiments. As shown in FIG. 5B,portions of the charge trapping dielectric 504 have been removed fromthe substrate 502. Specifically, the portions of charge trappingdielectric 504 not beneath structures 522 a and 522 b have been removed.According to some embodiments, the portions of the charge trappingdielectric 504 can be removed using any appropriate etching methodusing, instance, Cl2, KOH, TMAH (tetra-methyl-amino-hydroxyl), or usinggas phase etching with, for instance, H2, HCl, O2, H2O (vapor or gas),O3, HF, F2, and Carbon-Fluoride compounds with Cl2 and XeF2.Additionally, according to some embodiments, a combination of etchingproducts may be used.

In addition to depicting the removal of portions of the charge trappingdielectric 504, FIG. 5B depicts sidewall dielectrics 510 a ₁, 510 a ₂,510 b ₁, and 510 b ₂ (510 a ₂ and 510 b ₂ in FIG. 5B) that have beenformed on the sides of gate structures 522 a and 522 b. While FIG. 5Bdepicts the formation of the device 500 with sidewall dielectrics 510 a₁, 510 a ₂, 510 b ₁, and 510 b ₂ on each side of gate structures 522 aand 522 b, it is possible to omit the formation of some of the sidewallsdialectics. For instance, according to some embodiments, only sidewalldielectrics 510 a ₁ 510 b ₁ are formed. According to variousembodiments, the sidewall dielectrics 510 a ₁, 510 a ₂, 510 b ₁, and 510b ₂ may comprise a single layer dielectric or a multiple layerdielectric such as ONO, described above.

FIG. 5C depicts semiconductor device 500 at a different point during itsmanufacture according to various embodiments. As shown in FIG. 5C, aconducting layer 512 is formed substantially conformally over gatestructures 522 a and 522 b, however, this need not be the ease. Forinstance, according to some embodiments, conducting layer 512 may benon-conformal. According to various embodiments, the gate conductinglayer 512 may be disposed or deposited according to any appropriatewell-known method such as deposition. Deposition can comprise anyprocess that grows, coats, or transfers material onto a substrate. Somewell-known technologies include physical vapor deposition (PVD),chemical vapor deposition (CVD), electrochemical deposition (ECD),molecular beam epitaxy (MBE), atomic layer deposition (ALD), andplasma-enhanced CVD (PECVD), amongst others.

The conducting layer 512 includes a top portion 534 and one or morevertical portions 532. The top portion 534 lies above dividing line 530and the one or more vertical portions 532 lie below dividing lines 530.The vertical portion 534 is disposed adjacent to the sidewalldielectrics 510 a ₁, 510 a ₂, 510 b ₁, and 510 b ₂. For instance, asshown in FIG. 5C, vertical portion 532 is adjacent to sidewalldielectric 510 a _(i). Top portion 534 includes any portion of theconducting layer 512 that is disposed above dividing line 530. However,as shown in FIG. 5C, the top portion includes a portion of the caplayers 508 and the sidewall dielectrics 510 a ₁, 510 a ₂, 510 b ₁, and510 b ₂.

FIG. 5D depicts device 500 at a different point during its manufactureaccording to various embodiments. As shown in FIG. 5D, the top portion532 (e.g., the portion of the conducing layer 512 above dividing fine530) is removed creating three separate portions of conducting layer512: 514 a disposed to the left of gate structure 522 a; 514 b disposedto the right of gate structure 522 b; and 514 c disposed between gatestructures 522 a and 522 b. According to various embodiments, theseparate portions 514 a, 514 b, and 514 c of conducing layer 512 arecreated by planarization of the conducing layer 512 such that it isflush with cap layers 508 a and 508 b. According to various embodiments,the planarization comprises poly chemical mechanical planarization(CMP). Other suitable methods such as coat planarization material and adry etch-back. A thin oxide may optionally be disposed on device 500according to various embodiments.

FIG. 5E depicts device 500 at a different point during its manufactureaccording to various embodiments. As shown in FIG. 5E, portions 514 aand 514 b are etched to remove excess conducting layer 512 material.After the etching, the thin oxide is removed. At this point, thesubstrate to the left of portion 514 a and to the right of portion 514 bare doped as a drain so that portions 514 a and 514 b can function asselect gates. Additionally, portion 514 c is entirely removed fromdevice 500 with a mask that covers 510 a 1 and 510 b 1, and some of 506a and 506 b. While not necessary, it is also possible to remove sidewalldielectrics 510 a, and 51 b ₂, as depicted in FIG. 5F. At this point, ifdevice 500 will be used as a split gate memory cell, the substrate inbetween the gate structures 522 a and 522 b are doped as a sourcewhereby conductor layers 506 a and 506 b can function as memory gates.

FIG. 5G depicts device 500 at a different point during its manufactureaccording to various embodiments. As shown in FIG. 5G, the caps 508 aand 508 be have been removed from the gate structures 522 a and 522 b.Additionally, the now-select gates 514 a and 514 b are further etched toshorten them, if desired. With the removal of the caps 508 a and 508 b,the height of the select gates 514 a and 514 b is substantially the sameas the height of the gate structures 522 a and 522 b. However, accordingto some embodiments, it is possible that the height of the two is notexactly the same. For instance, as shown in FIG. 5G, the height ofmemory gate 522 a, h_(a2), is less than the height of the select gate514 a, h_(a1). The top of the now-memory gate 506 a _(t) is depicted asnot being flush with the top of select gate 514 a _(t) in FIG. 5G. Whilethis is an acceptable embodiment, it is also possible to form the tops506 a _(t) and 514 a _(t) as flush with one another. At this point, thecombination of gate structure 522 a and select gate 514 a as well as thecombination of gate structure 522 b and select gate 514 b can beconfigured to function as memory cells according to well-known methods.

FIG. 6 depicts a method 600 of forming a semiconductor device 500according to various embodiments. While the steps of method 600 will bediscussed with respect to FIGS. 5A-5G, the specific embodimentsdescribed therein should not be viewed as limiting. Indeed, any numberof other embodiments consistent with the spirit and scope of thisdisclosure are possible.

As shown in FIG. 6, a gate structure 522 is formed on a substrate 502 atstep 602. The gate structure 522 is formed over a charge trappingdielectric 504, which comprises several layers 504 a, 504 b, and 504 c.Layers 504 a, 504 b, and 504 c of the charge trapping dielectric 504comprise any suitable dielectric material such as, for instance andoxide. The gate structure 522 includes a conductor layer 506 disposedabove the charge trapping dielectric 504 and a cap layer 502 disposedabove the conductor layer 506. A sidewall dielectric 510 is formed onthe gate structure 522.

At step 604, a second conducting layer 512 are formed over the gatestructure 522. Conducting layer 512 is formed substantially conformallyover gate structure 522 or, in the alternative, non-conformallyaccording to various embodiments.

At step 606, the conducting layer 512 is planarized to remove the topportion of the conducting layer 512 thereby leaving the remainingconducing layer 512 flush with the top of conductor layer 506. Accordingto various embodiments, the planarization comprises poly chemicalmechanical planarization (CMP). Other suitable methods such as coatplanarization material and a dry etch-back can be used. A thin oxide mayoptionally be deposited on device 500 at this point according to variousembodiments.

At step 608, the poly is further etched to remove excess drain-side poly514 c and the source side poly 514 a is further etched to remove excessat step 610 with a mask. The cap 508 is removed from the gate structureat step 612.

Embodiments of the present invention have been described above with theaid of functional building blocks illustrating the implementation ofspecified functions and relationships thereof. The boundaries of thesefunctional building blocks have been arbitrarily defined herein for theconvenience of the description. Alternate boundaries can be defined solong as the specified functions and relationships thereof areappropriately performed.

The foregoing description of the specific embodiments will so fullyreveal the general nature of the invention that others can, by applyingknowledge within the skill of the art, readily modify and/or adapt forvarious applications such specific embodiments, without undueexperimentation, without departing from the general concept of thepresent invention. Therefore, such adaptations and modifications areintended to be within the meaning and range of equivalents of thedisclosed embodiments, based on the teaching and guidance presentedherein. It is to be understood that the phraseology or terminologyherein is for the purpose of description and not of limitation, suchthat the terminology or phraseology of the present specification is tohe interpreted by the skilled artisan in light of the teachings andguidance. Additionally, it should be understood that none of theexamples or explanations contained herein arc meant to convey that thedescribed embodiments have been actually reduced to practice.

The breadth and scope of the present invention should not be limited byany of the above-described exemplary embodiments, but should be definedonly in accordance with the following claims and their equivalents.

1-17. (canceled)
 18. A semiconductor device, comprising: a substrate; agate structure formed on the substrate, wherein the gate structurecomprises a charge trapping dielectric formed between the substrate anda first poly layer, and a sidewall dielectric formed on a first side ofthe first poly layer; and a second poly layer adjacent to the gatestructure wherein the second poly layer includes a portion that is incontact with the sidewall dielectric.
 19. The device of claim 1, whereina height of the gate structure is substantially the same as a height ofthe second poly layer.
 20. The device of claim 1, wherein the device isconfigured as a split-gate memory cell.
 21. The device of claim 3,wherein the gate structure is configured as a memory gate.
 22. Thedevice of claim 3, wherein the second poly layer and the sidewalldielectric are configured as a select gate.
 23. The device of claim 1,wherein the charge trapping dielectric comprises an oxide layer and anitride layer.
 24. The device of claim 1, wherein the first sidewalldielectric comprises an oxide layer.
 25. A integrated circuit (IC)device, comprising: a substrate and a plurality of devices formed on thesubstrate, the plurality of devices comprising at least: a first deviceformed on the substrate, the first device comprising: a first gatestructure, the first gate structure comprising a first charge trappingdielectric formed between the substrate and a first poly layer, and afirst sidewall dielectric formed on a first side of the first polylayer; and a second poly layer adjacent to the first gate structurewherein the second poly layer is in contact with the first sidewalldielectric; and a second device formed on the substrate, the seconddevice comprising: a second gate structure, the second gate structurecomprising a second charge trapping dielectric formed between thesubstrate and a third poly layer, and a second sidewall dielectricformed on a second side of the third poly layer; and a fourth poly layeradjacent to the second gate structure wherein the fourth poly layer isin contact with the second sidewall dielectric.
 26. The IC device ofclaim 8, wherein the first device further comprises a third side of thefirst poly layer which is on the opposite side of the first poly layerfrom the first sidewall dielectric, and the second device furthercomprises a fourth side of the third poly layer which is on the oppositeside of the third poly layer from the second sidewall dielectric, andwherein the first device and the second device are disposed on thesubstrate such that the third side of the first poly layer and thefourth side of the third poly layer are adjacent but not in directcontact.
 27. The IC device of claim 9, wherein the substrate disposedbetween the third side of the first poly layer and the fourth side ofthe third poly layer is configured to act as a source to the firstdevice and the second device.
 28. The IC device of claim 10, wherein thefirst device and the second device are configured as split-gate memorycells.
 29. The IC device of claim 11, wherein the first gate structureis configured as a first memory gate and the second gate structure isconfigured as a second memory gate.
 30. The IC device of claim 11,wherein the second poly layer and the first sidewall dielectric areconfigured as a first select gate, and wherein the fourth poly layer andthe second sidewall dielectric are configured as a second select gate.31. The IC device of claim 9, wherein the first device further comprisesa third sidewall dielectric formed on the third side of the first polylayer and wherein the second device further comprises a fourth sidewalldielectric formed on the fourth side of the third poly layer.
 32. The ICdevice of claim 8, wherein a height of the second poly layer and aheight of the fourth poly layer are substantially the same.
 33. The ICdevice of claim 16, wherein a height of the first gate structure, theheight of the second poly layer, a height of the second gate structure,and the height of the fourth poly layer are substantially the same. 34.A method of forming an integrated circuit (IC) device, comprising:forming, on a substrate, a first gate structure comprising a firstcharge trapping dielectric formed between the substrate and a first polylayer, and a first sidewall dielectric on a first side of the first polylayer; forming, on the substrate, adjacent to but not in direct contactwith the first gate structure, a second gate structure comprising asecond charge trapping dielectric formed between the substrate and asecond poly layer, and a second sidewall dielectric on a second side ofthe second poly layer; forming a third poly layer over the first gatestructure and over the second gate structure such that the third polylayer includes a first vertical portion that is in contact with thefirst sidewall dielectric, a second vertical portion that is in contactwith the second sidewall dielectric, and a top portion; and removing thetop portion.
 35. The method of claim 17, further comprising forming afirst memory gate from the first gate structure and a second memory gatefrom the second gate structure, and forming a first select gate from thefirst vertical portion and a second select gate from the second verticalportion.
 36. The method of claim 18, further comprising forming thefirst gate structure and the second gate structure such that a thirdside of the first poly layer which is on the opposite side of the firstpoly layer from the first sidewall dielectric and a fourth side of thethird poly layer which is on the opposite side of the third poly layerfrom the second sidewall dielectric are adjacent but not in directcontact.
 37. The method of claim 19, further comprising configuring thesubstrate between the first device and the second device to be a sourceto the first memory gate and the second memory gate.